This invention relates to information storage circuits, and more particularly to information storage circuits hardened to single event upsets.
A Single Event Upset (SEU) changes the value of a bit in a logic circuit. Single Event Upsets (SEUs) are caused by natural radiation sources, such as alpha particles and cosmic rays, interacting with the transistors included in a logic circuit. Microprocessors are comprised of logic circuits, and SEUs are a significant source of soft errors in these circuits. Any circuit node to which either a drain or source of a metal-oxide semiconductor (MOS) transistor is attached can exhibit a random change of voltage due to an SEU, which may cause a soft error in the operation of the microprocessor. The consequence of a soft error is an unwanted change of state of a microprocessor beyond control of a user program, leading to processing and storage of corrupted data, modification of the execution flow and, in the worst case, crash of a system. Soft errors, as opposed to hard errors, do not cause physical damage to the underlying circuitry, although erroneous operation caused by soft errors can finally result in physical damage to the circuit itself or other parts of the system. As the dimensions of the transistors that make up microprocessors decrease and as the operating voltages of the microprocessors decrease, soft-errors due to SEUs are likely to increase. For many systems, such as server computers, airplanes, trains, and cars, which are controlled by microprocessors, reliable operation of the microprocessors is required, even in the presence of radiation and SEUs. A microprocessor failure in these systems can result in a system failure.
Combinational (memoryless) logic circuits can recover from an SEU because the inputs to those circuits are driven by uncorrupted signals. An SEU in a combinational circuit can lead to a soft error if a subsequent memory circuit reads a wrong output during the period of time while the combinational circuit is still recovering. Such an event requires synchronization of an SEU with the clock signal of the memory circuit and low logic depth from the upset node to the input port of the memory circuit. That is why combinational circuits exhibit a much lower soft error rate compared to memory circuits. However, memory devices, such as random-access memory (RAM) devices may not recover from an SEU.
FIG. 1 is a schematic diagram of a prior art RAM memory cell. The cell can store one information bit represented by one of the two possible stable states of the cell. In the first state, node 100 stores a logic value 0 and node 103 stores 1. In the second state, node 100 stores 1 and node 103 stores 0. A voltage change induced by an SEU on node 100 can propagate to node 103. When this occurs, the original information on nodes 100 and 103 is lost and the stored information bit is inverted. Therefore, this cell is not immune to SEUs.
FIG. 2 is a schematic diagram of a prior art hardened RAM cell. Nodes 200 and 203 correspond to node 100 of the RAM memory cell of FIG. 1, and nodes 206 and 209 correspond to node 103 of the RAM memory cell of FIG. 1. If one of the nodes 200, 203, 206, or 209 experiences an SEU, it will recover to its original state because of redundant information stored in the associated nodes. In one stable state, nodes 200 and 203 store 0 and nodes 206 and 209 store 1. An SEU at node 206 can change its logic value to 0. As a result, node 200 will be pulled up by a pMOS transistor with its gate attached to node 206. Logic values at nodes 203 and 209 remain intact. At the same time as node 206 is being pulled up by the pMOS transistor with its gate connected to node 203, node 200 is being pulled down by an nMOS transistor with its gate connected to node 209. This simultaneous recovery action forces nodes 200 and 206 to resume their original logic values prior to the SEU and the cell completely recovers. Unfortunately, duplication of a storage circuit, which is required by this solution, is very expensive in terms of area on an electronic chip. Moreover, the cell does not provide any means of filtering out temporarily incorrect data appearing at storage nodes 200, 203, 206, or 209 during the period of time while the cell is still recovering. The spurious output data can lead to soft errors in subsequent memory circuits if this cell is employed in a latch.
FIG. 3 is a schematic diagram of a prior art unhardened latch. The information stored at node 300 is maintained via a clocked keeper latch comprising gates 303, 306, 309, 312, and 315. An SEU at node 300 or 321 can change the state of the latch and destroy the stored information. One approach to reducing the effects of SEUs in latched storage devices rests on the characterization of SEUs as short duration pulse events. The amplitude of a short duration pulse that must traverse a long time constant resistor-capacitor (RC) circuit is decreased, and circuits following the RC circuit remain unaffected. For example, a one picosecond pulse event that must traverse an RC circuit having a one microsecond time constant has little effect at the output of the RC circuit. By applying this theory to the problem of hardening latches to SEUs, one or more long RC time constant circuits can be inserted between latch nodes, such as nodes 300 and 317 and nodes 321 and 324, to suppress short duration SEUs at nodes 300 and 317. Unfortunately, for some embodiments inserting a circuit having a long RC time constant between the nodes of a latch increases the write time of the latch.
For these and other reasons there is a need for the present invention.
A latch comprises a first latch and a second latch coupled to the first latch. The second latch is capable of hardening the latch to a single event upset.